ARM Cortex-A57
| General information | |
|---|---|
| Launched | 2012 |
| Designed by | ARM Holdings |
| Cache | |
| L1 cache | 80 KiB (48 KiB I-cache with parity, 32 KiB D-cache with ECC) per core |
| L2 cache | 512 KiB to 2 MiB |
| L3 cache | none |
| Architecture and classification | |
| Instruction set | ARMv8-A |
| Physical specifications | |
| Cores |
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| Products, models, variants | |
| Product code name |
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| History | |
| Successor | ARM Cortex-A72 |
The ARM Cortex-A57 is a central processing unit implementing the ARMv8-A 64-bit instruction set designed by ARM Holdings. The Cortex-A57 is an out-of-order superscalar pipeline. It is available as SIP core to licensees, and its design makes it suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC).