ARM Cortex-A75
| General information | |
|---|---|
| Launched | 2017 |
| Designed by | ARM Holdings |
| Max. CPU clock rate | to 3.0 GHz |
| Cache | |
| L1 cache | 128 KB (64 KB I-cache with parity, 64 KB D-cache) per core |
| L2 cache | 256–512 KB |
| L3 cache | 1–4 MB |
| Architecture and classification | |
| Application | Mobile Network Infrastructure Automotive designs Servers |
| Instruction set | ARMv8.2-A |
| Physical specifications | |
| Cores |
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| Products, models, variants | |
| Product code name |
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| History | |
| Predecessors | ARM Cortex-A73 ARM Cortex-A72 ARM Cortex-A17 |
| Successor | ARM Cortex-A76 |
The ARM Cortex-A75 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings's Sophia design centre. The Cortex-A75 is a 3-wide decode out-of-order superscalar pipeline. The Cortex-A75 serves as the successor of the Cortex-A73, designed to improve performance by 20% over the A73 in mobile applications while maintaining the same efficiency.