PDP-11 architecture
| Designer | Digital Equipment Corporation |
|---|---|
| Bits | 16-bit |
| Introduced | 1970 |
| Design | CISC |
| Type | Register–register Register–memory Memory–memory |
| Encoding | Variable (2 to 6 bytes) |
| Branching | Condition code |
| Endianness | Mixed (little-endian for 16-bit integers) |
| Extensions | EIS, FIS, FPP, CIS |
| Open | No |
| Successor | VAX |
| Registers | |
| General-purpose | 8 × 16-bit |
| Floating point | 6 × 64-bit floating-point registers if FPP present |
The PDP-11 architecture is a 16-bit CISC instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC). It is implemented by central processing units (CPUs) and microprocessors used in PDP-11 minicomputers. It was in wide use during the 1970s, but was eventually overshadowed by the more powerful VAX architecture in the 1980s.