ARM Cortex-X2
| General information | |
|---|---|
| Launched | 2021 |
| Designed by | Arm |
| Performance | |
| Max. CPU clock rate | 2.85 GHz to 3.0 GHz |
| Address width | 40-bit |
| Cache | |
| L1 cache | 128 KiB (64 KiB I-cache with parity, 64 KiB D-cache) per core |
| L2 cache | 256–1024 KiB per core |
| L3 cache | 512 KiB – 16 MiB (optional) |
| Architecture and classification | |
| Microarchitecture | ARM Cortex-X2 |
| Instruction set | ARMv9.0-A |
| Physical specifications | |
| Cores |
|
| Products, models, variants | |
| Product code name |
|
| Variant | |
| History | |
| Predecessor | ARM Cortex-X1 |
| Successor | ARM Cortex-X3 |
The ARM Cortex-X2 is a CPU implementing the ARMv9-A 64-bit instruction set designed by ARM Holdings' Austin design centre as part of ARM's Cortex-X Custom (CXC) program.
It forms part of Arm's Total Compute Solutions 2021 (TCS21) along with Arm's Cortex-A710, Cortex-A510, Mali-G710 and CoreLink CI-700/NI-700.