IBM S/370-XA registers
General Registers 0–15
|
|
Two's complement value |
|
|
0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
31 |
|
|
Control Registers 0–15
|
|
See Principles of Operation: 4-6–4-8 |
|
|
0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
31 |
|
|
Floating-Point Registers 0–6
|
|
S |
Biased exponent |
Mantissa |
|
|
0 |
1 |
|
|
|
|
|
7 |
8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
31 |
|
|
|
Mantissa (continued) |
|
|
32 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
63 |
|
|
Extended Architecture Extended Control mode PSW: 4-5–4-6
|
|
0 |
R |
0 |
0 |
0 |
T |
I O |
E X |
Key |
1 |
M |
W |
P |
S |
0 |
CC |
Program Mask |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
|
0 |
1 |
2 |
|
4 |
5 |
6 |
7 |
8 |
|
|
11 |
12 |
13 |
14 |
15 |
16 |
17 |
18 |
19 |
20 |
|
|
23 |
24 |
|
|
|
|
|
|
31 |
|
|
|
A |
Instruction Address |
|
|
32 |
33 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
63 |
|
S/370-XA EC mode PSW abbreviations
| Bits |
Field |
Meaning |
| 1 |
R |
PER Mask |
| 5 |
T |
DAT mode |
| 6 |
IO |
I/O Mask; subject to channel mask in CR2 |
| 7 |
EX |
External Mask; subject to external subclass mask in CR0 |
| 8–11 |
Key |
PSW key |
| 12 |
E=1 |
Extended Control mode |
| 13 |
M |
Machine-check mask |
| 14 |
W |
Wait state |
| 15 |
P |
Problem state |
| 16 |
S |
Address-Space Control 0=primary-space mode 1=Secondary-space mode |
| 18–19 |
CC |
Condition Code |
| 20–23 |
PM |
Program Mask
| Bit |
Meaning |
| 20 |
Fixed-point overflow |
| 21 |
Decimal overflow |
| 22 |
Exponent underflow |
| 23 |
Significance |
|
| 32 |
A |
Addressing mode 0=24-bit; 1=31-bit |
| 33–63 |
IA |
Instruction Address |
|
- IBM documentation numbers the bits from high order to low order; the most significant (leftmost) bit is designated as bit number 0.
|
IBM System/370-XA is an instruction set architecture introduced by IBM in 1983 for the IBM 308X processors.: 198 It extends the IBM System/370 architecture to support 31-bit virtual and physical addresses, and includes a redesigned I/O architecture.